The present invention relates to a method and apparatus for plating a substrate and, more particularly, to a technology for forming wiring and the like by electrolytic plating.
As a conventional wiring material for an LSI formed on a semiconductor substrate made of silicon, aluminum has been used primarily. As semiconductor integrated circuits have increased in the degree of integration and in operating speed in recent years, however, copper having lower electric resistance than aluminum and high resistance to electromigration (EM) has received attention as a wiring material. Examples of a method for forming a copper film include an electrolytic plating method as disclosed in, e.g., Japanese Laid-Open Patent Publication No. 2001-316869.
Referring to the drawings, a description will be given herein below to a conventional method for plating a substrate by electrolytic plating.
FIGS. 10A to 10C are schematic diagrams illustrating the individual process steps of the conventional method for plating a substrate.
First, as shown in FIG. 10A, a substrate 11 held in a horizontal state by a substrate holding mechanism 12 is immersed in a plating solution 10 in circulation. Then, the substrate 11 is rotated together with the substrate holding mechanism 12 at a speed of rotation of 30 rpm by using a control device (not shown). An electrode 13 for contacting the surface of the substrate 11 to be plated and a seal 17 (not shown) for contacting the surface to be plated in such a manner as to protect the electrode 13 from the plating solution 10 have been mounted on the substrate holding mechanism 12.
At this time, bubbles 15 each having a size of about several tens of micrometers stagnate under the surface of the rotating substrate 11 to be plated, as shown in FIGS. 10A and 10B, while the bubbles 15 are expelled from the surface of the substrate 11 to be plated to the outside of the substrate holding mechanism 12 by the rotation of the substrate 11 and the ascending current 10a of the plating solution 10. The expelling of the bubbles 15 is completed within 1 second. Whether or not the expelling of the bubbles 15 has been completed is checked by examining a variation in resistance value with an extremely small current applied when the semiconductor substrate 11 is immersed in the plating solution 10.
When the semiconductor substrate is brought into contact with the plating solution, extremely small bubbles each having a size of about several micrometers or less are adsorbed to the surface to be plated such as, e.g., the surface of a Cu seed film. In the conventional plating method and plating apparatus, however, the extremely small bubbles cannot be removed. Consequently, the problem occurs during the subsequent plating growth that the plating growth is hindered at the portions of the surface to be plated to which the bubbles are adsorbed.
FIGS. 11A and 11B, FIGS. 12A and 12B, and FIGS. 13A to 13C are views for illustrating the problem encountered in the conventional method for plating a substrate.
Specifically, as shown in FIG. 11A, an interlayer insulating film 22, a TaN barrier film 23, and a Cu seed film 24 are deposited successively on the substrate 21. When the substrate 21 is then immersed in a plating solution 26 with the surface of the Cu seed film 24 to be plated facing downward, the bubbles 25 are adsorbed to the surface of the Cu seed film 24. If a plating process is performed in this state, a plate film 27 is formed with the bubbles 25 adsorbed to the surface of the Cu seed film 24 so that a pit defect (pit-type defect) 28 and voids 29 are formed finally in the plate film 27, as shown in FIG. 11B.
If particles 30 are adhered onto the Cu seed film 24 at the time at which the interlayer insulating film 22, the TaN barrier film 23, and the Cu seed film 24 are deposited on the substrate 21 as shown in FIG. 12A, the following problem arises. That is, when the substrate 21 is brought into contact with the plating solution 26, the bubbles 25 are adsorbed to the surface of the Cu seed film 24 with the particles 30 serving as nuclei so that the pit defect 28 and the voids 29 are formed in the plate film 27 in the same manner as in the foregoing case, as shown in FIG. 12B.
If these defects, specifically the pit defect 28, the voids 29, and the like occur in, e.g., a wiring portion composed of the plate film 27 buried in the insulating film 22, a contact portion composed of the plate film 27 filled in a hole reaching a lower-layer wire, or the like, reliability degradation such as deteriorated resistance to electromigration occurs.
There are other cases where problems as shown in FIGS. 13A to 13C are encountered in the conventional method for plating a substrate.
As shown in FIG. 13A, a first interlayer insulating film 52 is formed on a substrate 51, while a lower-layer wire composed of a TaN barrier film 53 and a Cu plate film 54 is buried in the first interlayer insulating film 52. Here, a depression resulting from the foregoing pit defect or the like is formed in the Cu plate film 54. If a SiN film 55 and a second interlayer insulating film 56 are formed on the first interlayer insulating film 52 including the lower-layer wire, therefore, a depression 57 resulting from the foregoing depression may also be formed in the surface of the second interlayer insulating film 56.
If such a depression 57 occurs in a region formed with a wide wire (upper-layer wire), a serious fault is less likely to occur in the portion formed with the depression 57. If the depression 57 is transferred onto the region of the second interlayer insulating film 56 other than the upper-layer wire formation region, however, a faulty pattern may be formed during lithography for forming a trench for an upper-layer wire due to the concave configuration of the depression 57. Otherwise, the following problem occurs when an upper-layer wire 58 composed of a TaN barrier film 58a and a Cu plate film 58b is buried in the second interlayer insulating film 56, as shown in FIG. 13B. That is, the residues of the TaN film 59a and the Cu film 59b resulting from the polishing of a wiring material are filled also in the depression 57 to form a conductive portion 59, which causes an inter-wire short circuit in the upper-layer wire 58, as shown in FIG. 13C. FIG. 13C is a plan view corresponding to FIG. 13B. In other words, FIG. 13B is a cross-sectional view taken along the line B–B′ of FIG. 13C.